AM79C970A datasheet(96/219 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C970A

LED and also have an EEPROM, it might be necessary

to buffer the

LED3 circuit from the EEPROM connection.

When an LED circuit is directly connected to the

EEDO/

LED3/SRD pin, then it is not possible for most

Microwire EEPROM devices to sink enough IOL to

maintain a valid low level on the EEDO input to the

PCnet-PCI II controller. In applications where an

EEPROM is not needed, the

LED3 pin may be directly

connected to an LED circuit. The PCnet-PCI II controller

LED3 pin driver will be able to sink enough current to

properly drive the LED circuit.

Each LED can be programmed through a BCR register

to indicate one or more of the following network status or

activities: Collision Status, Full-Duplex Link Status,

Half-Duplex Link Status, Jabber Status, Magic Packet

Status, Receive Match, Receive Polarity, Receive

Status and Transmit Status. The LED pins can be con-

figured to operate in either open-drain mode (active low)

or in totem-pole mode (active high). The output can be

stretched to allow the human eye to recognize even

short events that last only several microseconds. After

H_RESET, the four LED outputs are configured in the

following manner:

Table 13. LED Default Configuration

LED Output

Indication

Driver Mode

Pulse Stretch

LNKST

Link Status

Open Drain – Active Low

Enabled

LED1

Receive Status

Open Drain – Active Low

Enabled

LED2

Receive Polarity

Open Drain – Active Low

Enabled

LED3

Transmit Status

Open Drain – Active Low

Enabled

For each LED register, each of the status signals is

ANDed with its enable signal, and these signals are all

ORed together to form a combined status signal. Each

LED pins combined status signal can be programmed to

run to a pulse stretcher, which consists of a 3-bit shift

shift register is normally at logic 0. The OR gate output

for each LED register asynchronously sets all three bits

of its shift register when the output becomes asserted.

The inverted output of each shift register is used to con-

trol an LED pin. Thus the pulse stretcher provides 2–3

clocks of stretched LED output, or 52 ms to 78 ms.

19436A-44

COL

COLE

FDLS

FDLSE

JAB

JABE

LNKST

LNKSTE

RCV

RCVE

RCVM

RCVME

RXPOL

RXPOLE

XMT

XMTE

Pulse

Stretch

MFS

MFSE

Figure 41. LED Control Logic

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