AD7730LBR datasheet(35/52 Pages) AD

35 / 52 page

AD7730/AD7730L

REV. A

–35–

SERIAL INTERFACE

The AD7730’s programmable functions are controlled via a set

of on-chip registers. Access to these registers is via the part’s

serial interface. After power-on or

RESET, the device expects a

write to its Communications Register. The data written to this

read or a write operation and also determines to which register

this read or write operation occurs. Therefore, write access to

one of the control registers on the part starts with a write opera-

tion to the Communications Register followed by a write to the

selected register. Reading from the part’s on-chip registers can

take the form of either a single or continuous read. A single read

from a register consists of a write to the Communications Regis-

ter (with RW1 = 0 and RW0 = 1) followed by the read from the

specified register. To perform continuous reads from a register,

write to the Communications Register (with RW1 = 1 and

RW0 = 0) to place the part in continuous read mode. The speci-

fied register can then be read from continuously until a write

operation to the Communications Register (with RW1 = 1 and

RW0 = 1) which takes the part out of continuous read mode.

When operating in continuous read mode, the part is continu-

ously monitoring its DIN line. The DIN line should therefore

be permanently low to allow the part to stay in continuous read

mode. Figure 5 and Figure 6, shown previously, indicate the

correct flow diagrams when reading and writing from the

AD7730’s registers.

The AD7730’s serial interface consists of five signals,

CS,

SCLK, DIN, DOUT and

RDY. The DIN line is used for

transferring data into the on-chip registers while the DOUT line

is used for accessing data from the on-chip registers. SCLK is

the serial clock input for the device and all data transfers (either

on DIN or DOUT) take place with respect to this SCLK signal.

Write Operation

The transfer of data into the part is to an input shift register. On

completion of a write operation, data is transferred to the speci-

fied register. This internal transfer will not take place until the

correct number of bits for the specified register have been

loaded to the input shift register. For example, the transfer of

data from the input shift register takes place after eight serial

clock cycles for a DAC Register write, while the transfer of data

from the input shift register takes place after 24 serial clock

cycles when writing to the Filter Register. Figure 18 shows a

timing diagram for a write operation to the input shift register of

the AD7730. With the POL input at a logic high, the data is

latched into the input shift register on the rising edge of SCLK.

With the POL input at a logic low, the data is latched into the

input shift register on the falling edge of SCLK.

Figure 18 also shows the

CS input being used to decode the

write operation to the AD7730. However, this

CS input can be

used in a number of different ways. It is possible to operate the

part in three-wire mode where the

CS input is tied low perma-

nently. In this case, the SCLK line should idle high between

data transfer when the POL input is high and should idle low

between data transfers when the POL input is low. For POL = 1,

the first falling edge of SCLK clocks data from the microcontrol-

ler onto the DIN line of the AD7730. It is then clocked into the

input shift register on the next rising edge of SCLK. For POL = 0,

the first clock edge that clocks data from the microcontroller

onto the DIN line of the AD7730 is a rising edge. It is then

clocked into the input shift register on the next falling edge of

SCLK.

In other microcontroller applications which require a decoding

of the AD7730,

CS can be generated from a port line. In this

case,

CS would go low well in advance of the first falling edge of

SCLK (POL = 1) or the first rising edge of SCLK (POL = 0).

Clocking of each bit of data is as just described.

In DSP applications, the SCLK is generally a continuous clock.

In these applications, the

CS input for the AD7730 is generated

from a frame synchronization signal from the DSP. For proces-

sors with the rising edge of SCLK as the active edge, the POL

input should be tied high. For processors with the falling edge of

SCLK as the active edge, the POL input should be tied low. In

these applications, the first edge after

CS goes low is the active

edge. The MSB of the data to be shifted into the AD7730 must

be set up prior to this first active edge.

Read Operation

The reading of data from the part is from an output shift regis-

ter. On initiation of a read operation, data is transferred from

the specified register to the output shift register. This is a paral-

lel shift and is transparent to the user. Figure 19 shows a timing

diagram for a read operation from the output shift register of the

AD7730. With the POL input at a logic high, the data is clocked

out of the output shift register on the falling edge of SCLK.

With the POL input at a logic low, the data is clocked out of the

output shift register on the rising edge of SCLK.

Figure 19 also shows the

CS input being used to decode the

read operation to the AD7730. However, this

CS input can be

used in a number of different ways. It is possible to operate the

part in three-wire mode where the

CS input is permanently tied

low. In this case, the SCLK line should idle high between data

transfer when the POL input is high, and should idle low be-

tween data transfers when the POL input is low. For POL = 1,

the first falling edge of SCLK clocks data from the output shift

into the microcontroller on the next rising edge of SCLK. For

POL = 0, the first clock edge that clocks data from the AD7730

onto the DOUT line is a rising edge. It is then clocked into the

microcontroller on the next falling edge of SCLK.

In other microcontroller applications which require a decoding

of the AD7730,

CS can be generated from a port line. In this

case,

CS would go low well in advance of the first falling edge of

SCLK (POL = 1) or the first rising edge of SCLK (POL = 0).

Clocking of each bit of data is as just described.

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