AD7730LBR datasheet(30/52 Pages) AD

30 / 52 page

AD7730/AD7730L

–30–

REV. A

Internally in the AD7730, the coefficients are normalized before

being used to scale the words coming out of the digital filter.

The offset calibration register contains a value which, when

normalized, is subtracted from all conversion results. The gain

calibration register contains a value which, when normalized, is

multiplied by all conversion results. The offset calibration coeffi-

cient is subtracted from the result prior to the multiplication by

the gain coefficient.

The AD7730 offers self-calibration or system calibration facili-

ties. For full calibration to occur on the selected channel, the on-

chip microcontroller must record the modulator output for two

different input conditions. These are “zero-scale” and “full-

scale” points. These points are derived by performing a conver-

sion on the different input voltages provided to the input of the

modulator during calibration. The result of the “zero-scale”

calibration conversion is stored in the Offset Calibration Regis-

ter for the appropriate channel. The result of the “full-scale”

calibration conversion is stored in the Gain Calibration Register

for the appropriate channel. With these readings, the microcon-

troller can calculate the offset and the gain slope for the input to

output transfer function of the converter. Internally, the part

works with 33 bits of resolution to determine its conversion

result of either 16 bits or 24 bits.

The sequence in which the zero-scale and full-scale calibration

occurs depends upon the type of full-scale calibration being

performed. The internal full-scale calibration is a two-step cali-

bration that alters the value of the Offset Calibration Register.

Thus, the user must perform a zero-scale calibration (either

internal or system) after an internal full-scale calibration to correct

the Offset Calibration Register contents. When using system

full-scale calibration, it is recommended that the zero-scale

calibration (either internal or system) is performed first.

Since the calibration coefficients are derived by performing a

conversion on the input voltage provided, the accuracy of the

calibration can only be as good as the noise level the part pro-

vides in normal mode. To optimize the calibration accuracy, it

is recommended to calibrate the part at its lowest output rate

where the noise level is lowest. The coefficients generated at any

output update rate will be valid for all selected output update

rates. This scheme of calibrating at the lowest output update

rate does mean that the duration of calibration is longer.

Internal Zero-Scale Calibration

An internal zero-scale calibration is initiated on the AD7730 by

writing the appropriate values (1, 0, 0) to the MD2, MD1 and

MD0 bits of the Mode Register. In this calibration mode with a

unipolar input range, the zero-scale point used in determining

the calibration coefficients is with the inputs of the differential

pair internally shorted on the part (i.e., AIN(+) = AIN(–) =

Externally-Applied AIN(–) voltage). The PGA is set for the

selected gain (as per the RN1, RN0 bits in the Mode Register)

for this internal zero-scale calibration conversion.

The calibration is performed with dc excitation regardless of the

status of the ac bit. The duration time of the calibration de-

pends upon the CHP bit of the Filter Register. With CHP = 1,

the duration is 22

× 1/Output Rate; with CHP = 0, the duration

is 24

× 1/Output Rate. At this time the MD2, MD1 and MD0

bits in the Mode Register return to 0, 0, 0 (Sync or Idle Mode

for the AD7730). The

RDY line goes high when calibration is

initiated and returns low when calibration is complete. Note

that the part has not performed a conversion at this time; it has

simply performed a zero-scale calibration and updated the Off-

set Calibration Register for the selected channel. The user must

write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1, MD0 bits of the

Mode Register to initiate a conversion. If

RDY is low before (or

goes low during) the calibration command write to the Mode

before

RDY goes high to indicate that calibration is in progress.

Therefore,

RDY should be ignored for up to one modulator

cycle after the last bit of the calibration command is written to

the Mode Register.

For bipolar input ranges in the internal zero-scale calibrating

mode, the sequence is very similar to that just outlined. In this

case, the zero-scale point is exactly the same as above but since

the part is configured for bipolar operation, the output code for

zero differential input is 800000 Hex in 24-bit mode.

The internal zero-scale calibration needs to be performed as

one part of a two part full calibration. However, once a full

calibration has been performed, additional internal zero-scale

calibrations can be performed by themselves to adjust the

part’s zero-scale point only. When performing a two step full

calibration care should be taken as to the sequence in which the

two steps are performed. If the internal zero-scale calibration is

one part of a full self-calibration, then it should take place after

an internal full-scale calibration. If it takes place in association

with a system full-scale calibration, then this internal zero-scale

calibration should be performed first.

Internal Full-Scale Calibration

An internal full-scale calibration is initiated on the AD7730 by

writing the appropriate values (1, 0, 1) to the MD2, MD1 and

MD0 bits of the Mode Register. In this calibration mode, the

full-scale point used in determining the calibration coefficients is

with an internally-generated full-scale voltage. This full-scale

voltage is derived from the reference voltage for the AD7730

and the PGA is set for the selected gain (as per the RN1, RN0

bits in the Mode Register) for this internal full-scale calibration

conversion.

In order to meet the post-calibration numbers quoted in the

specifications, it is recommended that internal full-scale calibra-

tions be performed on the 80 mV range. This applies even if the

subsequent operating mode is on the 10 mV, 20 mV or 40 mV

input ranges.

The internal full-scale calibration is a two-step sequence that

runs when an internal full-scale calibration command is written

to the AD7730. One part of the calibration is a zero-scale cali-

bration and as a result, the contents of the Offset Calibration

The user must therefore perform a zero-scale calibration (either

internal or system) AFTER the internal full-scale calibration.

This zero-scale calibration should be performed at the operating input

range.

This means that internal full-scale calibrations cannot be

performed in isolation.

The calibration is performed with dc excitation regardless of the

status of the ac bit. The duration time of the calibration de-

pends upon the CHP bit of the Filter Register. With CHP = 1,

the duration is 44

× 1/Output Rate; with CHP = 0, the duration

is 48

× 1/Output Rate. At this time the MD2, MD1 and MD0

bits in the Mode Register return to 0, 0, 0 (Sync or Idle Mode

for the AD7730). The

RDY line goes high when calibration is

initiated and returns low when calibration is complete. Note

that the part has not performed a conversion at this time. The

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