AD7730LBR datasheet(36/52 Pages) AD

36 / 52 page

AD7730/AD7730L

–36–

REV. A

In DSP applications, the SCLK is generally a continuous clock.

In these applications, the

CS input for the AD7730 is generated

from a frame synchronization signal from the DSP. In these

applications, the first edge after

CS goes low is the active edge.

The MSB of the data to be shifted into the DSP must be set up

prior to this first active edge. Unlike microcontroller applica-

tions, the DSP does not provide a clock edge to clock the MSB

from the AD7730. In this case, the

CS of the AD7730 places

the MSB on the DOUT line. For processors with the rising edge

of SCLK as the active edge, the POL input should be tied high.

In this case, the DSP takes data on the rising edge. If

CS goes

low while SCLK is low, the MSB is clocked out on the DOUT

line from the

CS. Subsequent data bits are clocked from the

falling edge of SCLK. For processors with the falling edge of

SCLK as the active edge, the POL input should be tied low. In

this case, the DSP takes data on the falling edge. If

CS goes low

while SCLK is high, the MSB is clocked out on the DOUT line

from the

CS. Subsequent data bits are clocked from the rising

edge of SCLK.

Figure 18. Read Cycle Timing Diagram

Figure 19. Write Cycle Timing Diagram

The

RDY line is used as a status signal to indicate when data is

ready to be read from the AD7730’s data register.

RDY goes

low when a new data word is available in the data register. It is

reset high when a read operation from the data register is com-

plete. It also goes high prior to the updating of the data register

to indicate when a read from the data register should not be

initiated. This is to ensure that the transfer of data from the data

twice from the output register even though the

RDY line returns

high after the first read operation. Care must be taken, however,

to ensure that the read operations are not initiated as the next

output update is about to take place.

For systems with a single data line, the DIN and DOUT lines

on the AD7730 can be connected together, but care must be

taken in this case not to place the part in continuous read mode

as the part monitors DIN while supplying data on DOUT and

as a result, it may not be possible to take the part out of its

continuous read mode.

DOUT

SCLK

(POL = 1)

RDY

MSB

LSB

t10

SCLK

(POL = 0)

t5A

DIN

SCLK

(POL = 1)

MSB

t12

t15

LSB

t16

t14

t11

t13

SCLK

(POL = 0)

t14

t15

AD7730LBR Fiches technique(PDF) 36 Page - Analog Devices

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