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M24M01-R Fiches technique(PDF) 28 Page - STMicroelectronics

No de pièce M24M01-R
Description  1-Mbit serial I²C bus EEPROM
PDF  38 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24M01-R Fiches technique(HTML) 28 Page - STMicroelectronics

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DC and AC parameters
M24M01-R M24M01-DF
28/38
Doc ID 12943 Rev 10
Table 14.
400 kHz AC characteristics
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
-
400
kHz
tCHCL
tHIGH
Clock pulse width high
600
-
ns
tCLCH
tLOW
Clock pulse width low
1300
-
ns
tQL1QL2
(1)
1.
Characterized only, not tested in production.
tF
SDA (out) fall time
20(2)
2.
With CL = 10 pF.
300
ns
tXH1XH2
tR
Input signal rise time
(3)
3.
There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
(3)
ns
tXL1XL2
tF
Input signal fall time
(3)
(3)
ns
tDXCH
tSU:DAT
Data in set up time
100
-
ns
tCLDX
tHD:DAT
Data in hold time
0
-
ns
tCLQX
(4)
4.
To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
tDH
Data out hold time
100(5)
5.
The previous product identified by process letter P was specified with tCLQX = 200 ns (min). Both values
offer a safe margin compared to the I2C specification recommendations.
-ns
tCLQV
(6)
6.
tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12.
tAA
Clock low to next data valid (access time)
-
900
ns
tCHDL
tSU:STA
Start condition setup time
600
-
ns
tDLCL
tHD:STA
Start condition hold time
600
-
ns
tCHDH
tSU:STO Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tWLDL
(7)(1)
7.
WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC
WC set up time (before the Start condition)
0
-
µs
tDHWH
(8)(1)
8.
WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC
WC hold time (after the Stop condition)
1
-
µs
tW
tWR
Internal Write cycle duration
-
5
ms
tNS
(1)
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-80(9)
9.
The previous product identified by process letter A or B was specified with tNS = 100 ns (max).
ns



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