HT66F13 datasheet(39/173 Pages) HOLTEK

39 / 173 page

EnteringtheSLEEP0Mode

There is only one way for the device to enter the SLEEP0 Mode and that is to execute the HALT

instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT

and LVD both off. When this instruction is executed under the conditions described above, the

following will occur:

· The system clock, WDT clock and Time Base clock will be stopped and the application program

will stop at the

²HALT² instruction.

· The Data Memory contents and registers will maintain their present condition.

· The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB

clock or from the system clock.

· The I/O ports will maintain their present conditions.

· In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,

will be cleared.

EnteringtheSLEEP1Mode

There is only one way for the device to enter the SLEEP1 Mode and that is to execute the

²HALT²

instruction in the application program with the IDLEN bit in SMOD register equal to

²0² and the WDT

or LVD on. When this instruction is executed under the conditions described above, the following will

occur:

· The system clock and Time Base clock will be stopped and the application program will stop at the

²HALT² instruction, but the WDT or LVD will remain with the clock source coming from the fSUB

clock.

· The Data Memory contents and registers will maintain their present condition.

· The WDT will be cleared and resume counting if the WDT clock source is selected to come from the

fSUB clock as the WDT is enabled.

· The I/O ports will maintain their present conditions.

· In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,

will be cleared.

EnteringtheIDLE0Mode

There is only one way for the device to enter the IDLE0 Mode and that is to execute the

²HALT²

instruction in the application program with the IDLEN bit in SMOD register equal to

²1² and the

FSYSON bit in WDTC register equal to

²0². When this instruction is executed under the conditions

described above, the following will occur:

· The system clock will be stopped and the application program will stop at the

²HALT² instruction,

but the Time Base clock and fSUB clock will be on.

· The Data Memory contents and registers will maintain their present condition.

· The WDT will be cleared and resume counting if the WDT clock source is selected to come from the

fSUB clock and the WDT is enabled. The WDT will stop if its clock source originates from the system

clock.

· The I/O ports will maintain their present conditions.

· In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,

will be cleared.

Rev.1.10

February9,2011

HT66F13/HT66F14/HT66F15

EnhancedA/DFlashType MCU

HT66F13 Fiches technique(PDF) 39 Page - Holtek Semiconductor Inc

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