STM8L101F1P3ATR datasheet(50/81 Pages) STMICROELECTRONICS

50 / 81 page

Electrical parameters

STM8L101xx

50/81

Doc ID 15275 Rev 11

9.3.6

I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All

unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

Table 26.

I/O static characteristics (1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage(2)

Standard I/Os

VSS-0.3

0.3 x VDD

True open drain I/Os

VSS-0.3

0.3 x VDD

VIH

Input high level voltage (2)

Standard I/Os

0.70 x VDD

-VDD+0.3

True open drain I/Os

VDD < 2 V

0.70 x VDD

5.2

True open drain I/Os

VDD ≥ 2 V

5.5

Vhys

Schmitt trigger voltage hysteresis (3)

Standard I/Os

200

True open drain I/Os

250

Ilkg

Input leakage current (4)

VSS≤VIN≤VDD

Standard I/Os

50 (5)

VSS≤VIN≤VDD

True open drain I/Os

200(5)

VSS≤VIN≤VDD

PA0 with high sink LED

driver capability

200(5)

RPU

Weak pull-up equivalent resistor(6)

VIN=VSS

CIO

(7)

I/O pin capacitance

VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

The max. value may be exceeded if negative current is injected on adjacent pins.

Not tested in production.

RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in

Figure 22).

Data guaranteed by Design, not tested in production.

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