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STM8L15 Fiches technique(PDF) 91 Page - STMicroelectronics |
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STM8L15 Fiches technique(HTML) 91 Page - STMicroelectronics |
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91 / 122 page ![]() STM8L151xx, STM8L152xx Electrical parameters Doc ID 15962 Rev 5 91/122 Figure 32. Typical NRST pull-up current Ipu vs VDD The reset network shown in Figure 33 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 40. Otherwise the reset is not taken into account internally. Figure 33. Recommended NRST pin configuration 0.01 μF EXTERNAL RESET CIRCUIT STM8L Filter RPU VDD INTERNAL RESET RSTIN |
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