430 datasheet(72/100 Pages) INTEL

72 / 100 page

Land Listing and Signal Descriptions

Datasheet

RS[2:0]#

Input

RS[2:0]# (Response Status) are driven by the response agent (the

agent responsible for completion of the current transaction), and

must connect the appropriate pins/lands of all processor FSB

agents.

SKTOCC#

Output

SKTOCC# (Socket Occupied) will be pulled to ground by the

processor. System board designers may use this signal to determine

if the processor is present.

SMI#

Input

SMI# (System Management Interrupt) is asserted asynchronously

by system logic. On accepting a System Management Interrupt, the

processor saves the current state and enter System Management

Mode (SMM). An SMI Acknowledge transaction is issued, and the

processor begins program execution from the SMM handler.

If SMI# is asserted during the de-assertion of RESET#, the

processor will tri-state its outputs.

STPCLK#

Input

STPCLK# (Stop Clock), when asserted, causes the processor to

enter a low power Stop-Grant state. The processor issues a Stop-

Grant Acknowledge transaction, and stops providing internal clock

signals to all processor core units except the FSB and APIC units.

The processor continues to snoop bus transactions and service

interrupts while in Stop-Grant state. When STPCLK# is de-asserted,

the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus clock;

STPCLK# is an asynchronous input.

TCK

Input

TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port).

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

TDO

Output

TDO (Test Data Out) transfers serial test data out of the processor.

TDO provides the serial output needed for JTAG specification

support.

TESTHI[13:0]

Input

TESTHI[13:0] must be connected to the processor’s appropriate

power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal

description) through a resistor for proper processor operation. See

Section 2.4 for more details.

Table 25.

Signal Description ( (Sheet 7 of 9))

Name

Type

Description

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