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H8SX1663 Fiches technique(PDF) 286 Page - Renesas Technology Corp

No de pièce H8SX1663
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX1663 Fiches technique(HTML) 286 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 234 of 1102
REJ09B0294-0100
6.10.8
Controlling Precharge Cycle
The number of precharge cycles (Tp) can be selected from one to four clock cycles by bits TPC1
and TPC0 in DRACCR. Set the bit according to the DRAM to be used and the frequency of this
LSI so that the number of precharge cycle can be optimal.
Figure 6.42 shows an access timing example when two Tp cycles are specified.
The setting of bits TPC1 and TPC0 affect the Tp cycle of a refresh cycle.
T
p1
T
p2
T
r
T
c1
T
c2
Address bus
Row address
Column address
B
φ
RAS
LUCAS
LLCAS
WE
OE (RD)
WE
OE (RD)
Data bus
High
High
Read
Write
Data bus
BS
RD/
WR
Figure 6.42 Access Timing Example of Two Precharge Cycles (RAST = 0 and CAST = 0)



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