H8SX1663 datasheet(209/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 157 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

RAST

R/W

RAS Assertion Timing Select

Selects whether the

RAS signal is asserted at the rising

edge or falling edge of the B

φ signal in the Tr cycle

during a DRAM access. The relationship between this

bit and

RAS assertion timing is shown in figure 6.4.

When SDRAM is used, the setting of this bit does not

affect operation.

0: RAS signal is asserted at the falling edge of the Bf

signal in the Tr cycle

1: RAS signal is asserted at the rising edge of the Bf

signal in the Tr cycle



Reserved

The initial value should not be changed.

CAST

R/W

Column Address Output Cycle Count Select

Selects whether the number of column address output

cycles is two or three during a DRAM access.

When SDRAM is used, the setting of this bit does not

affect operation.

0: Column address is output for two cycles

1: Column address is output for three cycles

R/W

Burst Access Enable

Enables or disables a burst access to the

DRAM/SDRAM. The DRAM/SDRAM is accessed in

high-speed page mode. When DRAM with the EDO

page mode is used, connect the

OE signal of this LSI to

the

OE signal of DRAM.

0: DRAM/SDRAM is accessed with full access

1: DRAM/SDRAM is accessed in high-speed page

mode

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