H8SX1663 datasheet(174/1158 Pages) RENESAS

No de pièce	H8SX1663

Description	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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Fabricant	RENESAS [Renesas Technology Corp]

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 122 of 1102

REJ09B0294-0100

Table 5.5

Number of Execution States in Interrupt Handling Routine

Object of Access

External Device

8-Bit Bus

16-Bit Bus

Symbol

On-Chip

Memory

2-State

Access

3-State

Access

2-State

Access

3-State

Access

Vector fetch S

12 + 4m

6 + 2m

Instruction fetch S

6 + 2m

3 + m

Stack manipulation S

12 + 4m

6 + 2m

[Legend]

Number of wait cycles in an external device access.

5.6.5

DTC and DMAC Activation by Interrupt

The DTC and DMAC can be activated by an interrupt. In this case, the following options are

available:

• Interrupt request to the CPU

• Activation request to the DTC

• Activation request to the DMAC

• Combination of the above

For details on interrupt requests that can be used to activate the DTC and DMAC, see table 5.2,

section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC).

Figure 5.6 shows a block diagram of the DTC, DMAC, and interrupt controller.

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