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H8SX1663 Fiches technique(PDF) 963 Page - Renesas Technology Corp

No de pièce H8SX1663
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX1663 Fiches technique(HTML) 963 Page - Renesas Technology Corp

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Section 21 Flash Memory (0.18-
µm F-ZTAT Version)
Rev.1.00 Jun. 07, 2006 Page 911 of 1102
REJ09B0294-0100
21.7.3
User Program Mode
Programming/erasing of the user MAT is executed by downloading an on-chip program. The
programming/erasing flow is shown in figure 21.11.
Since high voltage is applied to the internal flash memory during programming/erasing, a
transition to the reset state or hardware standby mode must not be made during
programming/erasing. A transition to the reset state or hardware standby mode during
programming/erasing may damage the flash memory. If a reset is input, the reset must be released
after the reset input period (period of
RES = 0) of at least 100 µs.
When programming,
program data is prepared
Programming/erasing
procedure program is
transferred to the on-chip
RAM and executed
Programming/erasing
start
Programming/erasing
end
Exit RAM emulation mode beforehand. Download is not allowed
in emulation mode.
When the program data is adjusted in emulation mode, select
the download destination specified by FTDAR carefully. Make
sure that the download area does not overlap the emulation
area.
Programming/erasing is executed only in the on-chip RAM.
After programming/erasing is finished, protect the flash memory
by the hardware protection.
1.
2.
3.
4.
Figure 21.11 Programming/Erasing Flow



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