H8SX1663 datasheet(449/1158 Pages) RENESAS

No de pièce	H8SX1663

Description	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

Fabricant	RENESAS [Renesas Technology Corp]

Site Internet	http://www.renesas.com

Logo

449 / 1158 page

Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 397 of 1102

REJ09B0294-0100

8.2

DTC has the following registers.

• DTC mode register A (MRA)

• DTC mode register B (MRB)

• DTC source address register (SAR)

• DTC destination address register (DAR)

• DTC transfer count register A (CRA)

• DTC transfer count register B (CRB)

These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the

CPU. The contents of these registers are stored in the data area as transfer information. When a

DTC activation request occurs, the DTC reads a start address of transfer information that is stored

in the data area according to the vector address, reads the transfer information, and transfers data.

After the data transfer, it writes a set of updated transfer information back to the data area.

• DTC enable registers A to E, G, and H (DTCERA to DTCERE, DTCERG, and DTCERH)

• DTC control register (DTCCR)

• DTC vector base register (DTCVBR)

H8SX1663 Fiches technique(PDF) 449 Page - Renesas Technology Corp