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STPCATLAS Fiches technique(PDF) 26 Page - STMicroelectronics

No de pièce STPCATLAS
Description  X86 Core PC Compatible System-on-Chip for Terminals
PDF  111 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPCATLAS Fiches technique(HTML) 26 Page - STMicroelectronics

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PIN DESCRIPTION
26/111
Issue 1.0 - July 24, 2002
2.3. SIGNAL DETAIL
The muxing between ISA, LOCAL BUS and
PCMCIA is performed by external strap options.
The resulting interface is then dynamically muxed
with the IDE Interface.
Table 2-4. Multiplexed Signals (on the same pin)
IDE Pin Name
ISA Pin Name
PCMCIA Pin Names
Local Bus Pin Name
DIORDY
IOCHRDY
-
DA[2]
LA[19]
= 0
DA[1:0]
LA[18:17]
A[25:24]
SCS3,SCS1
LA[23:22]
A[23:22]
PCS3,PCS1
LA[21:20]
A[21:20]
DD[15]
RMRTCCS#
ROMCS#
DD[14]
KBCS#
Hi-Z
DD[13:12]
RTCRW#, RTCDS#
Hi-Z
DD[11:0]
SA[19:8]
A[19:8]
SD[15:0]
D[15:0]
PD[15:0]
RTCAS
= 0
FCS0#
DEV_CLK
DEV_CLK
FCS1#
SA[3]
A[3]
PRDY
SA[2:0]
A[2:0]
IOCS#[2:0]
SMEMW#
VPP_PGM
PBE#[1]
IOCS16#
WP/IOIS16#
PBE#[0]
MASTER#
BVD1
PRD#
MCS16#
= 0
PWR#
DACK_ENC [2:0]
= 0x04
PA[2:0]
TC
= 0
PA[3]
SA[7:4]
A[7:4]
PA[7:4]
ZWS#
GPI#
PA[8]
GPIOCS#
VCC5_EN
PA[9]
IOCHCK#
BVD2
PA[10]
REF#
RESET
PA[11]
IOW#
IOWR#
PA[12]
IOR#
IORD#
PA[13]
MEMR#
= 0
PA[14]
ALE
= 0
PA[15]
AEN
WAIT#
PA[16]
BHE#
OE#
PA[17]
MEMW#
= 0
PA[18]
SMEMR#
VCC3_EN
PA[19]
DREQ_MUX#[1:0]
CE2#, CE1#
PA[21:20]
Hi-Z
Hi-Z
PA[22]
Hi-Z
VPP_VCC
PA[23]
Hi-Z
WE#
PA[24]
Hi-Z
REG#
IOCS#[7]
Hi-Z
READY#
IOCS#[6]
Hi-Z
CD1#, CD2#
IOCS#[5], IOCS#[4]
ISAOE# = 1
ISAOE# = 0
ISAOE# = 0
IOCS#[3]



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