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STLC5048 Fiches technique(PDF) 35 Page - STMicroelectronics |
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STLC5048 Fiches technique(HTML) 35 Page - STMicroelectronics |
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35 / 45 page ![]() 35/45 STLC5048 Figure 5. Figure 6. SLIC Control port timing SLIC CONTROL INTERFACE TIMING (dynamic configuration) Symbol Parameter Test Condition Min. Typ. Max. Unit Tcs Chip Select repetition rate 31.25 µs tcsw Chip select pulse width 3.9 µs tdcsl Data out valid to CS low 1.95 ns tscsh Data out held after CS high 1.95 ns tscsh Set up time Data in to CS high 50 ns thcsh Hold time data in to CS high 10 ns CCLK CS CI CO D00TL471 123 45678 tRC tFC tWCH tWCL 1 2 3 4 5 6 70 1 2 3 4 5 6 7 tDSD tDCD tHCS tSDC tHCD tSSC tSCS tHSC tCSO tDOA tDON 31.25 µs (32KHz) tDIV CS1 CS2 CS3 CS4 IO (OUT) IO (IN) OUT CH0 IN CH0 OUT CH1 IN CH1 OUT CH2 IN CH2 OUT CH3 IN CH3 OUT CH0 D99TL460 IN CH0 OUT CH1 IN CH1 tDII ELECTRICAL CHARACTERISTCS (continued) |
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