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STLC5048 Fiches technique(PDF) 23 Page - STMicroelectronics |
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STLC5048 Fiches technique(HTML) 23 Page - STMicroelectronics |
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23 / 45 page ![]() 23/45 STLC5048 TPA/B = These two bits are used to enable the DX outputs of the port A or/and B. According to the combination of these two bits the enabled port will be as follows: RPAB = 0: Port A enabled (DRA input selected) RPAB = 1: Port B enabled (DRB input selected) TE = 0: Transmit PCM data change on rising edge of MCLK TE = 1: Transmit PCM data change on falling edge of MCLK PC1-PC0 = Selection of the channel for the PCM access data via MCU. WR = 1: Setting this bit , receive PCM data writing via MCU (after A/ µ decoding) is enabled on selected channel and IPCM interrupt is generated every time FS signal becomes active, together to the set of the WRD bit in the PCMCTRL register. A data byte must be written every 125 µs, if data is not replaced the old value is inserted again but the PMW bit is set to 1 in the PCMCTRL register. RR = 1: Setting this bit, transmit PCM data reading (after A/ µ encoding) via MCU is enabled on selected channel and IPCM interrupt is generated every time that data are available, together to the set of the RRD bit in the PC- MCTRL register. A data byte must be read every 125 µS, if data is not read the new value is written in the PCM access register but the POW bit is set to 1 in the PCMCTRL register. Transmit Time Slot ch #0 (DXTS0) Addr=52h; Reset Value=00h EN0=0:Selected transmit time slot on DX output is in H.I. EN0=1:Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI0. T06..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI0 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most signifi- cant bits in the programmed time slot, the 8 least significant bits in the following time slot. Example: if T06..T00=00: TPB TPA Description 0 0 Both Ports disabled 0 1 Port A enabled 1 0 Port B enabled 1 1 Both ports enabled PC0 PC1 Description 0 0 Channel #0 selected 1 0 Channel #1 selected 0 1 Channel #2 selected 1 1 Channel #3 selected Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W 1 010010 EN0 T06 T05 T04 T03 T02 T01 T00 TS0 TS1 15 14 13 12 11 10 9876543210 |
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