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ST70235A Fiches technique(PDF) 23 Page - STMicroelectronics

No de pièce ST70235A
Description  ASCOTTM DMT TRANSCEIVER
PDF  28 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST70235A Fiches technique(HTML) 23 Page - STMicroelectronics

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Tests, Clock, JTAG Interface
– Mclk: Master Clock (35.328MHz) generated by
VCXO
– ATM receive interface, asynchronous clock gen-
erated by Utopia Master
– ATM transmit interface, asynchronous clock
generated by Utopia Master
– ATC clock (Pclk): external asynchronous clock
(synchronous with ATC in case of i960 specific
interface)
JTAG TP interface: Standard Test Access Port,
Used with the boundary scan for chip and board
testing. This JTAG TAP interface consists in 5
signals:
TDI, TDO, TCK & TMS.
TSRTB: Test Reset, reset the TAP controller.
TRSTB is an active low signal.
Table 8 : Boundary Scan Chain Sequence
Signal
Name
Sequence
Number
BS
Type
Ad[0]
IO2
B
Ad[1]
IO3
B
Ad[2]
IO4
B
Ad[3]
IO6
B
Ad[4]
IO7
B
Ad[5]
IO9
B
Ad[6]
IO10
B
Ad[7]
IO12
B
Ad[8]
IO13
B
Ad[9]
IO14
B
Ad[10]
IO16
B
Ad[11]
IO17
B
Ad[12]
IO19
B
Pclk
IO21
C
Ad[13]
IO23
B
Ad[14]
IO24
B
Ad[15]
IO25
B
Be1
IO27
I
Ale
IO28
C
Csb
IO30
I
Wr_Rdb
IO31
I
Rdyb
IO32
B
Obc_Type
IO33
I
Intb
IO34
O
Resetb
IO35
I
U_Rxdata[0]
IO38
B
U_Rxdata[1]
IO39
B
U_Rxdata[2]
IO41
B
U_Rxdata[3]
IO42
B
U_Rxdata[4]
IO44
B
U_Rxdata[5]
IO45
B
U_Rxdata[6]
IO47
B
U_Rxdata[7]
IO48
B
U_Rxaddr[0]
IO50
I
U_Rxaddr[1]
IO51
I
U_Rxaddr[2]
IO52
I
U_Rxaddr[3]
IO53
I
U_Rxaddr[4]
IO55
I
Gp_In[0]
IO56
I
Gp_In[1]
IO58
I
U_Rxrefb
IO60
O
U_Txrefb
IO61
I
U_Rxclk
IO63
C
U_Rxsoc
IO64
I
U_Rxclav
IO65
O
U_Rxenb
IO66
I
U_Txclk
IO68
C
U_Txsoc
IO69
I
U_Txclav
IO70
O
U_Txenb
IO71
I
U_Txdata[7]
IO74
I
U_Txdata[6]
IO75
I
Table 8 : Boundary Scan Chain Sequence
Signal
Name
Sequence
Number
BS
Type



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