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ST70235A Fiches technique(PDF) 22 Page - STMicroelectronics |
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ST70235A Fiches technique(HTML) 22 Page - STMicroelectronics |
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22 / 28 page ![]() ST70235A 22/28 Figure 20 : Transmit Interface Table 3 : Transmitted Bits Assigned to Signal / Time Slot Figure 21 : Receive Interface MCLK AFTXD Tv MCLK AFRXD Ts Th CLWD Tc Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFTXD[0] b0 b4 b8 b12 AFTXD[1] b1 b5 b9 b13 AFTXD[2] b2 b6 b10 b14 AFTXD[3] b3 b7 b11 b15 Table 4 : Transmitted Bits Assigned to Signal / Time Slot Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFRXD[0] b0 b4 b8 b12 AFRXD[1] b1 b5 b9 b13 AFRXD[2] b2 b6 b10 b14 AFRXD[3] b3 b7 b11 b15 Table 5 : Master Clock (MCLK) AC Electrical Characteristics Symbol Parameter Minimum Typical Maximum Unit F Clock Frequency 35.328 MHz Tper Clock Period 28.3 ns Th Clock Duty Cycle 40 60 % Table 6 : AFTXD, AFTXED, CLWD AC Electrical Characteristics Symbol Parameter Minimum Typical Maximum Unit Tv Data Valid Time 0 13 ns Tc Data Valid Time 0 10 ns Table 7 : AFRXD AC Electrical Characteristics Symbol Parameter Minimum Typical Maximum Unit Ts Data setup Time 5 ns Th Data hold Time 5 ns |
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