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PSD913F2 Fiches technique(PDF) 41 Page - STMicroelectronics |
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PSD913F2 Fiches technique(HTML) 41 Page - STMicroelectronics |
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41 / 94 page ![]() Preliminary Information PSD9XX Family 37 The PSD9XX Functional Blocks (cont.) 9.3.3 Microcontroller Interface Examples Figures 14 through 18 show examples of the basic connections between the PSD9XX and some popular microcontrollers. The PSD9XX Control input pins are labeled as to the microcontroller function for which they are configured. The MCU interface is specified using the PSDsoft. 9.3.3.1 80C31 Figure 14 shows the interface to the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The microcontroller control signals PSEN, RD, and WR may be used for accessing the internal memory components and I/O Ports. The ALE input (pin PD0) latches the address. 9.3.3.2 80C251 The Intel 80C251 microcontroller features a user-configurable bus interface with four possible bus configurations, as shown in Table 19. Configuration 1 is 80C31 compatible, and the bus interface to the PSD9XX is identical to that shown in Figure 14. Configurations 2 and 3 have the same bus connection as shown in Figure 15. There is only one read input (PSEN) connected to the Cntl1 pin on the PSD9XX. The A16 connection to the PA0 pin allows for a larger address input to the PSD9XX. Configuration 4 is shown in Figure 16. The RD signal is connected to Cntl1 and the PSEN signal is connected to the CNTL2. The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0] are changing. The PSD9XX supports both modes. In Page Mode, the PSD bus timing is identical to Non-Page Mode except the address hold time and setup time with respect to ALE is not required. The PSD access time is measured from address A[7:0] valid to data in valid. |
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