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PSD913F2 Fiches technique(PDF) 74 Page - STMicroelectronics

No de pièce PSD913F2
Description  Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PDF  94 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD913F2 Fiches technique(HTML) 74 Page - STMicroelectronics

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PSD9XX Family
Preliminary Information
70
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tNLNH
Warm RESET Active Low Time (Note 1)
150
ns
tOPR
RESET High to Operational Device
120
ns
tNLNH-PO
Power On Reset Active Low Time
1
ms
Warm Reset, will abort and reset Flash
tNLNH-A
programming/erase cycles to Read mode.
25
µs
(Note 2)
Reset Pin Timing (5 V ± 10%)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
Vstby Detection to Vstbyon Output High
(Note 1)
20
µs
tBXBL
Vstby Off Detection to Vstbyon
Output Low
(Note 1)
20
µs
Vstbyon Timing (5 V ± 10%)
NOTE: 1. RESET will not reset Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle. For PSD934F2 and PSD954F2 only.
NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.
NOTE: 1. tCLCL is the CLKIN clock period.
Microcontroller Interface – PSD9XX AC/DC Parameters
(5V ± 10% Versions)
-70
-90
-15
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
tLVDV
ALE Access Time from
Power Down
80
90
150
ns
Maximum Delay from APD
tCLWH
Enable to Internal PDN
Using
15
* tCLCL (µs) (Note 1)
µs
Valid Signal
CLKIN Input
Power Down Timing (5 V ± 10%)



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