PSD913F2 datasheet(72/94 Pages) STMICROELECTRONICS

72 / 94 page

PSD9XX Family

Preliminary Information

NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

2. RD and PSEN have the same timing.

3. Any input used to select an internal PSD9XX function.

4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.

5. RD timing has the same timing as DS, LDS, and UDS signals.

-70

-90

-15

Turbo

Symbol

Parameter

Conditions

Min

Max

Min

Max

Min

Max

Off

Unit

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 3)

tLXAX

Address Hold Time

(Note 3)

tAVQV

Address Valid to Data Valid

(Note 3)

150

Add 10

t SLQV

CS Valid to Data Valid

100

150

RD to Data Valid 8-Bit Bus

(Note 5)

t RLQV

RD or PSEN to Data Valid 8-Bit Bus,

8031, 80251

(Note 2)

t RHQX

RD Data Hold Time

(Note 1)

tRLRH

RD Pulse Width

(Note 1)

tRHQZ

RD to Data High-Z

(Note 1)

tEHEL

E Pulse Width

tTHEH

R/W Setup Time to Enable

tELTL

R/W Hold Time After Enable

tAVPV

Address Input Valid to Address

(Note 4)

Output Delay

Read Timing (5 V ± 10% Versions)

Microcontroller Interface – PSD9XX AC/DC Parameters

(5V ± 10% Versions)

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