MPC8309CVMADFC datasheet(6/81 Pages) NXP

6 / 81 page

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Overview

— Card bus clock frequency up to 33.33 MHz.

— Supports 1-/4-bit SD and SDIO modes, 1-/4-bit modes

– Up to 133 Mbps data transfer for SD/SDIO/MMC cards using 4 parallel data lines

— Supports block sizes of 1 ~ 4096 bytes

•

Universal serial bus (USB) dual-role controller

— Designed to comply with Universal Serial Bus Revision 2.0 Specification

— Supports operation as a stand-alone USB host controller

— Supports operation as a stand-alone USB device

— Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.

Low speed is only supported in host mode.

•

FlexCAN module

— Full implementation of the CAN protocol specification version 2.0B

— Up to 64 flexible message buffers of zero to eight bytes data length

— Powerful Rx FIFO ID filtering, capable of matching incoming IDs

— Selectable backwards compatibility with previous FlexCAN module version

— Programmable loop-back mode supporting self-test operation

— Global network time, synchronized by a specific message

— Independent of the transmission medium (an external transceiver is required)

— Short latency time due to an arbitration scheme for high-priority messages

•

Dual I2C interfaces

— Two-wire interface

— Multiple-master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

—I2C1 can be used as the boot sequencer

•

DMA Engine1

— Support for the DMA engine with the following features:

– Sixteen DMA channels

– All data movement via dual-address transfers: read from source, write to destination

– Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations

– Channel activation via one of two methods (for both the methods, one activation per

execution of the minor loop is required):

– Explicit software initiation

– Initiation via a channel-to-channel linking mechanism for continuous transfers

(independent channel linking at end of minor loop and/or major loop)

– Support for fixed-priority and round-robin channel arbitration

– Channel completion reported via optional interrupt requests

— Support for scatter/gather DMA processing

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