MPC8309CVMADFC datasheet(48/81 Pages) NXP

48 / 81 page

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

JTAG

The following figure shows the SPI timing in slave mode (external clock).

Figure 37. SPI AC Timing in Slave Mode (External Clock) Diagram

The following figure shows the SPI timing in master mode (internal clock).

Figure 38. SPI AC Timing in Master Mode (Internal Clock) Diagram

21 JTAG

This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1™ (JTAG)

interface of the MPC8309.

21.1

JTAG DC Electrical Characteristics

The following table provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface

of the MPC8309.

Table 53. JTAG Interface DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

VOH

IOH =–6.0mA

2.4

—

Output low voltage

VOL

IOL =6.0 mA

—

0.5

Output low voltage

VOL

IOL =3.2 mA

—

0.4

SPICLK (Input)

tNEIXKH

tNEIVKH

tNEKHOV

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note:

The clock edge is selectable on SPI.

SPICLK (Output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note:

The clock edge is selectable on SPI.

tNIIVKH

MPC8309CVMADFC Fiches technique(PDF) 48 Page - NXP Semiconductors

MPC8309CVMADFC Fiches technique(HTML) 48 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Fiches technique Télécharger

Lien URL