APEX20KC datasheet(44/90 Pages) ALTERA

44 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 28. APEX 20KC I/O Banks

Notes to Figure 28:

(1)

For more information on placing I/O pins in LVDS blocks, refer to the “Guidelines for Using LVDS Blocks” section

in Application Note 120 (Using LVDS in APEX 20KE Devices).

(2)

If the LVDS input and output blocks are not used for LVDS, they can support all of the I/O standards and can be

used as input, output, or bidirectional pins with VCCIO set to 3.3 V, 2.5 V, or 1.8 V.

Power Sequencing & Hot Socketing

Because APEX 20KC devices can be used in a mixed-voltage environment,

they have been designed specifically to tolerate any possible power-up

sequence. Therefore, the VCCIO and VCCINT power supplies may be

powered in any order.

LVDS Input

Block (2)

(1)

LVDS Output

Block (2)

(1)

Individual

Power Bus

I/O Bank 8

I/O Bank 1

I/O Bank 2

I/O Bank 3

I/O Bank 4

I/O Bank 5

I/O Bank 6

I/O Bank 7

Regular I/O Banks Support

■ LVPECL

■ LVTTL

■ LVCMOS

■ 2.5 V

■ 1.8 V

■ 3.3-V PCI

■ GTL+

■ HSTL

■ SSTL-2 Class I and II

■ SSTL-3 Class I and II

■ CTT

■ AGP

APEX20KC Fiches technique(PDF) 44 Page - Altera Corporation

APEX20KC Fiches technique(HTML) 44 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Fiches technique Télécharger

Lien URL