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ADS5294IPFPR Fiches technique(PDF) 18 Page - Texas Instruments |
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ADS5294IPFPR Fiches technique(HTML) 18 Page - Texas Instruments |
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18 / 82 page ![]() Frame Clock ACLK Freq = fCLKIN Input Clock CLKIN Freq = fCLKIN SAMPLE N-1 D13 (D0) Data bit in MSB First mode Data bit in LSB First mode Bit Clock LCLK Freq = 7 x fCLKIN Output Data CHnOUT Data rate = 14 x fCLKIN D11 (D0) D10 (D1) SAMPLE N tPROG T Input Signal ta Sample N Sample N+td td clock cycles latency D0 (D13) D13 (D0) D12 (D1) D11 (D2) D10 (D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 (D10) D2 (D11) SAMPLE N-td D1 (D12) Sample N+td+1 D1 (D12) D0 (D13) D13 (D0) D12 (D1) D11 (D2) D10 (D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 (D10) D2 (D11) D1 (D12) D0 (D13) D13 (D0) D12 (D1) D11 (D2) D10 (D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 (D10) D2 (D11) D1 (D12) D0 (D13) ta ADS5294 SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018 www.ti.com 18 Product Folder Links: ADS5294 Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Figure 3. 14-Bit 1-Wire LVDS Timing Diagram |
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