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ADS5294 Fiches technique(PDF) 7 Page - Texas Instruments |
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ADS5294 Fiches technique(HTML) 7 Page - Texas Instruments |
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7 / 82 page ![]() 1 2 3 4 5 6 7 9 10 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 34 33 32 30 28 27 26 25 36 35 40 39 38 37 29 31 80 79 78 77 67 69 71 73 74 76 61 62 64 70 66 65 68 63 72 75 IN2P IN2N IN3P IN3N AGND IN4P IN4N AVDD AGND RESET IN7N IN7P IN5N IN5P IN6N IN6P AGND AGND LVDD LGND OUT8A_N PD OUT8A_P OUT8B_N LGND LVDD OUT8B_P ADS529X 80 TQFP OUT7A_N OUT7A_P OUT7B_N OUT7B_P AVDD OUT2B_P OUT2B_N OUT2A_P OUT2A_N OUT1B_P OUT1B_N OUT1A_P OUT1A_N Thermal Pad (Can be tied to AGND) 60 59 58 57 56 55 54 52 51 53 50 49 48 47 46 45 44 43 42 41 7 ADS5294 www.ti.com SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018 Product Folder Links: ADS5294 Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated 7 Pin Configuration and Functions PFP Package 80-PIN TQFP With Thermal Pad Top View Pin Functions PIN DESCRIPTION NAME NO. AVDD 9, 52, 66, 71, 74 Analog power supply, 1.8 V AGND 3, 6, 55, 58, 61, 80 Analog ground VCM 68 Common-mode output pin, 0.95-V output. This pin can be configured as the external reference voltage (1.5 V) input pin as well. See Reg 0x42 and External Reference Mode of Operation. CLKN 73 Negative differential clock –Tie CLKN to GND for single-ended clock CLKP 72 Positive differential clock IN1P, IN1N 78, 79 Differential input signal, Channel 1 IN2P, IN2N 1, 2 Differential input signal, Channel 2 IN3P, IN3N 4, 5 Differential input signal, Channel 3 IN4P, IN4N 7, 8 Differential input signal, Channel 4 IN5P, IN5N 53, 54 Differential input signal, Channel 5 IN6P, IN6N 56, 57 Differential input signal, Channel 6 IN7P, IN7N 59, 60 Differential input signal, Channel 7 IN8P, IN8N 62, 63 Differential input signal, Channel 8 LCLKP, LCLKN 31, 32 Differential LVDS bit clock (7X) ACLKP, ACLKN 29, 30 Differential LVDS frame clock (1X) |
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