ADS5294 datasheet(3/82 Pages) TI2

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ADS5294

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SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

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Corrected typo in Table 1 ..................................................................................................................................................... 33

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Added note to EN_2WIRE bit. .............................................................................................................................................. 44

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Corrected typo in Table 17 ................................................................................................................................................... 55

Changes from Revision B (July 2012) to Revision C

Page

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Added cross-reference link for VCM pin................................................................................................................................. 7

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Added note for REFB pin under INT/EXT reference modes. ................................................................................................. 8

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Added note for REFT pin under INT/EXT reference modes. ................................................................................................. 8

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Changed the maximum rating of digital input pins RESET, SCLK, SDATA, SYNC, PD, CSZ to 3.6V.................................. 9

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Added test condition "Digital Filter Disabled" and changed "LVDS output rate" to "ADC CLK Frequency" in LVDS

Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital Filter Disabled . ........................... 14

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Added test condition "Digital Filter Disabled" and changed "LVDS output rate" to "ADC CLK Frequency" in LVDS

Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital Filter Disabled . ......................... 14

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Added note after LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Digital

Filter Disabled : The above LVDS timing spec is only valid when digital filters are disabled... ........................................... 14

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Added LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter

Enabled ................................................................................................................................................................................ 16

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Added LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter

Enabled ................................................................................................................................................................................ 16

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Added LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter

Enabled ................................................................................................................................................................................ 16

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Added a note related to EN_CUSTOM_FILT and changed formats in Table 9. .................................................................. 33

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Added PLL Operation Versus LVDS Timing before APPLICATION INFORMATION section ............................................ 35

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Added a note link to Reg.0x38 . ........................................................................................................................................... 44

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Changed 0xF[15] to 0xF0[15] in the description of Reg.0x42. ............................................................................................. 44

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Changed the Reg.0x46[11:8] formatting. ............................................................................................................................. 44

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Corrected the EN_RAMP address from 0x24 to 0x25 in the section of LVDS test patterns. ............................................. 47

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Changed "Note that these bits are functional only when the GLOBAL_EN_FILTER gets set to 1" to " Note that these

bits are functional only when the GLOBAL_EN_FILTER gets set to 1 and USE_FILTERn bit is set to 1” in the

section of Decimation Filter,. ............................................................................................................................................... 54

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Added a note related to EN_CUSTOM_FILT and changed formats inTable 17 . ................................................................ 55

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Changed Equation (5). ......................................................................................................................................................... 59

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Added register address in Table 23. .................................................................................................................................... 59

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Revised Figure 63 and moved the 2pF cap to the left hand side of the resistors. .............................................................. 66

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Added a note regarding the location of LVDS Rterm in the section of Input clock. ............................................................ 67

Changes from Revision A (November 2011) to Revision B

Page

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Changed the location of OUT A and OUT B in Figure 5 and Figure 6................................................................................. 20

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Added Figure 45 ................................................................................................................................................................... 31

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Replaced Table 9 (Decimation Filter Modes) with new Table 1 - Digital Filters................................................................... 33

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Deleted section: Synchronization Pulse ............................................................................................................................... 35

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Added EN_HIGH_ADDRS to Table 3................................................................................................................................... 40

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Moved EN_EXT_REF From: 0x0F To: 0xF0 in Table 3....................................................................................................... 45

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Added the section BIT-BYTE-WORD WISE OUTPUT. Added Figure 53 and Figure 54..................................................... 48

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Added section DIGITAL PROCESSING BLOCKS ............................................................................................................... 49

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Replaced Table 5 and Table 6 with new Table 17 - Digital Filters....................................................................................... 55

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Changed the SYNCHRONIZATION PULSE section ............................................................................................................ 58

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