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STM32L412C8I6TR Fiches technique(PDF) 24 Page - STMicroelectronics |
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STM32L412C8I6TR Fiches technique(HTML) 24 Page - STMicroelectronics |
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24 / 192 page ![]() Stop 1 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMP1, OPAMP1 USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMP1 USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) USB_FS(8) 3.25 µA w/o RTC 3.65 µA w RTC 5.7 µs in SRAM 7 µs in Flash Stop 2 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMP1 I2C3(7) LPUART1(6) LPTIMx (x = 1, 2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMP1 I2C3(7) LPUART1(6) LPTIMx (x = 1, 2) 710 nA w/o RTC 950 nA w RTC 5.8 µs in SRAM 8.3 µs in Flash Table 4. STM32L412xx modes overview (continued) Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time |
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