FS310 datasheet(29/40 Pages) TTELEC

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General Note

TT Electronics reserves the right to make changes in product specification without

notice or liability. All information is subject to TT Electronics’ own data and is

considered accurate at time of going to print.

TT Electronics | OPTEK Technology

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www.ttelectronics.com | sensors@ttelectronics.com

Rev C, 4/27/2023

Page 29

FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Interrupt Mask/Status Register (INTR: [0x0889])

Table 30. INTR register definition.

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

ISPS

ISLC

ISTA

ISTS

RESV

IMLC

IMTA

IMTS

Table 31. INTR field description.

Bits

Description

IMTS

Interrupt mask bits for thermal shutdown condition:

Thermal shutdown condition does not cause IRQZ = 0

Thermal shutdown condition does cause IRQZ = 0

IMTA

Interrupt mask bit for thermal alarm condition:

Thermal alarm condition does not cause IRQZ = 0

Thermal alarm condition does cause IRQZ = 0

IMLC

Interrupt mask bit for LED control loop out-of-regulation:

LED control loop out-of-regulation condition does not cause IRQZ = 0

LED control loop out-of-regulation condition does cause IRQZ = 0

RSRV

Reserved for future use

ISTS

Read-only interrupt status bit for thermal shutdown condition:

→ 1 if on-chip junction temperature exceeds 165°C

ISTA

Read-only interrupt status bit for thermal alarm condition:

→ 1 if on-chip junction temperature exceeds value encoded by TASET

ISLC

Read-only interrupt status bit for LED control loop out-of-regulation:

→ 1 if actual LED drive current exceeds 7/8 of the value encoded by ILED<6:0>

ISPS

Read-only interrupt status bit for power-up sequence:

→ 1 when VDD/VDDA voltage rises above power-on reset trip point

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