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Rev C, 4/27/2023

Page 11

© TT electronics plc

FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Pixel Array Control

Correct operation of the FS210/FS310 requires that its photoactive area, an array of 4,096 pixels (64 rows by 64 columns),

be configured to be consistent with the code wheel with which it is being used. Six aggregate photocurrents are produced

by the device’s photoactive area: the positive- and negative-sense photocurrents for the two quadrature-track outputs and

for the index-track output. Each pixel’s photocurrent either contributes to one of the six aggregate photocurrents (A+, A-,

B+, B-, Z+, Z-) or is shunted to ground, depending on how the pixel is configured.

The on-chip physical dimensions of each pixel are 36.2μm by 18.1μm, so the dimensions of the entire photoactive area are

2.32mm by 1.16mm.

Associated with each pixel is a single SRAM bit called a Pixel Control (PXC) bit, and associated with each pixel column are

four SRAM bits called a Column Configuration (CCFG) nibble. A column’s CCFG nibble selects the aggregate photocurrent

output to which the active pixels in that column contribute (A+, A-, B+, B-, Z+, Z-, or none). A pixel’s PXC bit controls

whether that pixel is active – i.e. its photocurrent contributes to the aggregate photocurrent output selected by the

column’s 4-bit control field – or inactive – i.e. its photocurrent is shunted to ground.

The 4,096 PXC bits, or 512 bytes, occupy the address range [0x000 – 0x1FF]. The 64 CCFG nibbles, or 32 bytes, occupy the

address range [0x400 – 0x41F]. The mapping of logical bytes and bits to physical columns and pixels is detailed below.

The PXC and CCFG bytes are volatile SRAM, so their contents are lost every time the device is power cycled. Therefore, the

desired contents must be stored off-chip in non-volatile storage somewhere in the system, and the system must contain a

means to copy the patterns from the off-chip non-volatile storage into the on-chip SRAM through the device’s I2C port

every time it is powered up. If the system contains a microcontroller with non-volatile storage outside the encoder module,

then this microcontroller can contain the non-volatized PXC and CCFG contents. If the system does not contain a

microcontroller with non-volatile storage outside the encoder module, then a non-volatile memory chip with an I2C

interface and at least 1Kbyte capacity, such as the M24C32S-FCU from ST, is required.

Table 5: Mapping of PXC and CCFG Registers to Pixel Location

Col. Grp. 000

Col. Grp. 100

Col. Grp. 001

Col. Grp. 101

Col. Grp. 010

Col. Grp. 110

Col. Grp. 011

Col. Grp. 111

Row 00

[0x0000]

[0x0004]

[0x0001]

[0x0005]

[0x0002]

[0x0006]

[0x0003]

[0x0007]

Row 01

[0x0008]

[0x000C]

[0x0009]

[0x000D]

[0x000A]

[0x000E]

[0x000B]

[0x000F]

Row 02

[0x0010]

[0x0014]

[0x0011]

[0x0015]

[0x0012]

[0x0016]

[0x0013]

[0x0017]

Row 03

[0x0018]

[0x001C]

[0x0019]

[0x001D]

[0x001A]

[0x001E]

[0x001B]

[0x001F]

Rows

04-59

…

…

…

…

…

…

…

…

Row 60

[0x01E0]

[0x01E4]

[0x01E1]

[0x01E5]

[0x01E2]

[0x01E6]

[0x01E3]

[0x01E7]

Row 61

[0x01E8]

[0x01EC]

[0x01E9]

[0x01ED]

[0x01EA]

[0x01EE]

[0x01EB]

[0x01EF]

Row 62

[0x01F0]

[0x01F4]

[0x01F1]

[0x01F5]

[0x01F2]

[0x01F6]

[0x01F3]

[0x01F7]

Row 63

[0x01F8]

[0x01FC]

[0x01F9]

[0x01FD]

[0x01FA]

[0x01FE]

[0x01FB]

[0x01FF]

CCFG

[0x0400 –

0x0403]

[0x0404 –

0x0407]

[0x0408 –

0x040B]

[0x040C –

0x040F]

[0x0410 –

0x0413]

[0x0414 –

0x0417]

[0x0418 –

0x041B]

[0x041C –

0x041F]