AS3953B datasheet(10/65 Pages) AMSOSRAM

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[v1-04] 2016-Jan-07

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AS3953B − Detailed Description

Figure 10:

System Block Diagram

Circuit

The AS3953B is composed of ISO 14443A PICC Analog Front-end

(PICC AFE), the ISO 14443A PICC Logic (PICC Logic), EEPROM,

SPI Interface, Level Shifters and Power Supply Manager Block

(Power Manager).

The PICC AFE is connected to an external tag coil, which forms

together with integrated resonant capacitor an LC tank with a

resonance at the external electromagnetic field frequency of

13.56 MHz. The PICC AFE has a built in rectifier and regulators.

Output of internal regulator is called VP_INT. It is used to supply

the PICC AFE and usually also the LOGIC and EEPROM (through

Power Supply Manager). Output of external regulator VP_REG

is available on a pin to supply some external circuitry.

Power Manager is controlling power supply of Logic and

EEPROM. The two blocks can be supplied either from VP_INT or

from VP_SPI (SPI power supply). In order to save current on VP_

SPI, VP_INT is used as power supply whenever it is available.

VP_SPI is only used when some activity is started over the SPI

and the VP_INT is too low to be used as a power supply.

The PICC Logic is responsible for PICC-to-PCD communication

up to the Level-4 (block transmission) of ISO 14443A. This

means that anti-collision and other low-level functionality are

implemented there.

The SPI Interface logic contains a 32 byte FIFO for block

transmission data which is exchanged on Level-4 of ISO 14443A

communication. It also contains some control and display

registers.

The EEPROM is used to store the UID, the housekeeping data

(configuration and control bits) and user data. It can be

accessed from both sides (RFID and SPI).

Detailed Description

ISO 14443A

Reader

AS3953B

Microcontroller

SPI

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