PCF8812USLASH2 datasheet(21/36 Pages) PHILIPS

21 / 36 page

2000 Nov 22

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8812

Notes

1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load.

2. Internal clock.

3. fSCLK = 0 means no serial clock.

4. During power-down all static currents are switched off.

5. If external VLCD; the display load current is not transmitted to IDD.

6. Tolerance depend on the temperature; (typical null at Tamb =27 °C, maximum tolerance values are measured at the

temperate range limit, maximum tolerance is proportional to VLCD).

7. For TC1 to TC3.

14 AC CHARACTERISTICS

VDD = 2.5 to 5.5 V; VSS =0V; VLCD = 4.5 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise speciﬁed.

LCD supply voltage generator

VLCD

VLCD tolerance internally

generated

VDD1 = 2.8 V; VLCD = 7.6 V;

fSCLK = 0; Tamb =25 °C;

display-load = 10

µA;

notes 3, 6 and 7

−300

+300

VLCD temperature coefﬁcient VDD1 = 2.8 V; fSCLK =0;

Tamb = −20 to +70 °C;

display load = 10

µA; note 3

coefficient 0

−

× 10−3

−

°C

coefficient 1

−−0.76 × 10−3

−

°C

coefﬁcient 2

−−1.05 × 10−3

−

°C

coefﬁcient 3

−−2.10 × 10−3

−

°C

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fOSC

oscillator frequency

VDD1 = 2.8 V;

Tamb = −20 to +70 °C

kHz

fclk(ext)

external clock frequency

kHz

fframe

frame frequency

fOSC or fclk(ext) = 38 kHz;

note 1

−

tVHRL

VDD to RES LOW

see Fig.16

−

µs

tRW

RES LOW pulse width

see Fig.16

500

−−

Serial bus timing characteristics

fSCLK

clock frequency

VDD1 = 3.0 V ±10%; all

signal timing is based on

20% to 80% of VDD and a

maximum rise and fall time

of 10 ns

−

4.00

MHz

tcyc

clock cycle time

250

−−

tPWH1

SCLK pulse width HIGH

100

−−

tPWL1

SCLK pulse width LOW

100

−−

tS2

SCE set-up time

−−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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