MPC8560CPXAPDB datasheet(7/108 Pages) FREESCALE

7 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Overview

— Ability to start and flow control each DMA channel from external 3-pin interface

— Ability to launch DMA from single write transaction

•

PCI/PCI-X controller

— PCI 2.2 and PCI-X 1.0 compatible

— 64- or 32-bit PCI port supports at 16 to 66 MHz

— 64-bit PCI-X support up to 133 MHz

— Host and agent mode support

— 64-bit dual address cycle (DAC) support

— PCI-X supports multiple split transactions

— Supports PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses

— Supports posting of processor-to-PCI and PCI-to-memory writes

— PCI 3.3-V compatible

— Selectable hardware-enforced coherency

•

Power management

— Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O

— Supports power saving modes: doze, nap, and sleep

— Employs dynamic power management, which automatically minimizes power consumption of blocks

when they are idle.

•

System performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter-specific events

— Supports 64 reference events that can be counted on any of the 8 counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

•

System access port

— Uses JTAG interface and a TAP controller to access entire system memory map

— Supports 32-bit accesses to configuration registers

— Supports cache-line burst accesses to main memory

— Supports large block (4-Kbyte) uploads and downloads

— Supports continuous bit streaming of entire block for fast upload and download

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IEEE 1149.1-compliant, JTAG boundary scan

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783 FC-PBGA package

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