MPC8560CPXAPDB datasheet(40/108 Pages) FREESCALE

40 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Local Bus

Figure 16 provides the AC test load for the local bus.

Figure 16. Local Bus AC Test Load

Figure 17 through Figure 22 show the local bus signals.

Local bus clock to output high

impedance for LAD/LDP

TSEC2_TXD[6:5] = 00

tLBKHOZ2

—

TSEC2_TXD[6:5] = 11

(default)

1.5

Notes:

1.The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock

reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the

tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.

2.All timings are in reference to local bus clock for DLL bypass mode.

3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at OVDD/2.

4.All signals are measured from OVDD/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OVDD of

the signal in question for 3.3-V signaling levels.

5.Input timings are measured at the pin.

6.The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number

of local bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].

7.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current

delivered through the component pin is less than or equal to the leakage current specification.

Table 31. Local Bus General Timing Parameters - DLL Bypassed (continued)

Parameter

POR Configuration

Symbol 1

Min

Max

Unit

Notes

Output

OVDD/2

RL = 50 Ω

Z0 = 50 Ω

MPC8560CPXAPDB Fiches technique(PDF) 40 Page - Freescale Semiconductor, Inc

MPC8560CPXAPDB Fiches technique(HTML) 40 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL