| Moteur de recherche de fiches techniques de composants électroniques |
|
MPC8560CPXAPDB Fiches technique(PDF) 6 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8560CPXAPDB Fiches technique(HTML) 6 Page - Freescale Semiconductor, Inc |
|
6 / 108 page ![]() MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 6 Freescale Semiconductor Overview — Up to eight-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller — Three protocol engines available on a per chip select basis: – General purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit) • Two three-speed (10/100/1Gb) Ethernet controllers (TSECs) — Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers — Support for different Ethernet physical interfaces: – 10/100/1Gb Mbps IEEE 802.3 GMII – 10/100 Mbps IEEE 802.3 MII – 10 Mbps IEEE 802.3 MII – 1000 Mbps IEEE 802.3z TBI – 10/100/1Gb Mbps RGMII/RTBI — Full- and half-duplex support — Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models — 9.6-Kbyte jumbo frame support — RMON statistics support — 2-Kbyte internal transmit and receive FIFOs — MII management interface for control and status — Programmable CRC generation and checking — Ability to force allocation of header information and buffer descriptors into L2 cache. • OCeaN switch fabric — Four-port crossbar packet switch — Reorders packets from a source based on priorities — Reorders packets to bypass blocked packets — Implements starvation avoidance algorithms — Supports packets with payloads of up to 256 bytes • Integrated DMA controller — Four-channel controller — All channels accessible by both the local and remote masters — Extended DMA functions (advanced chaining and striding capability) — Support for scatter and gather transfers — Misaligned transfer capability — Interrupt on completed segment, link, list, and error — Supports transfers to or from any local memory or I/O port — Selectable hardware-enforced coherency (snoop/no-snoop) |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |