SC1100 datasheet(39/348 Pages) NSC

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Signal Definitions (Continued)

C/BE3#

V26

I/O

Multiplexed Command and Byte Enables. During the

address phase of a transaction when FRAME# is active,

C/BE[3:0]# define the bus command. During the data

phase, C/BE[3:0]# are used as byte enables. The byte

enables are valid for the entire data phase and determine

which byte lanes carry meaningful data. C/BE0# applies

to byte 0 (LSB) and C/BE3# applies to byte 3 (MSB).

D11

C/BE2#

R26

D10

C/BE1#

G24

C/BE0#

E24

INTA#

AD26

PCI Interrupts. The SC1100 provides inputs for the

optional “level-sensitive” PCI interrupts (also known in

industry terms as PIRQx#). These interrupts can be

mapped to IRQs of the internal 8259A interrupt control-

lers using PCI Interrupt Steering Registers 1 and 2

(F0 Index 5Ch and 5Dh).

---

INTB#

W24

---

INTC#

Y24

GPIO19

INTD#

V24

---

PAR

H24

I/O

Parity. Parity generation is required by all PCI agents.

The master drives PAR for address- and write-data

phases. The target drives PAR for read-data phases. Par-

ity is even across AD[31:0] and C/BE[3:0]#.

For address phases, PAR is stable and valid one PCI

clock after the address phase. It has the same timing as

AD[31:0] but is delayed by one PCI clock.

For data phases, PAR is stable and valid one PCI clock

after either IRDY# is asserted on a write transaction or

after TRDY# is asserted on a read transaction.

Once PAR is valid, it remains valid until one PCI clock

after the completion of the data phase. (Also see

PERR#.)

D12

FRAME#

P25

I/O

Frame Cycle. Frame is driven by the current master to

indicate the beginning and duration of an access.

FRAME# is asserted to indicate the beginning of a bus

transaction. While FRAME# is asserted, data transfers

continue. FRAME# is deasserted when the transaction is

in the final data phase.

---

IRDY#

P26

I/O

Initiator Ready. IRDY# is asserted to indicate that the

bus master is able to complete the current data phase of

the transaction. IRDY# is used in conjunction with

TRDY#. A data phase is completed on any PCI clock in

which both IRDY# and TRDY# are sampled as asserted.

During a write, IRDY# indicates that valid data is present

on AD[31:0]. During a read, it indicates that the master is

prepared to accept data. Wait cycles are inserted until

both IRDY# and TRDY# are asserted together.

D14

TRDY#

N25

I/O

Target Ready. TRDY# is asserted to indicate that the tar-

get agent is able to complete the current data phase of

the transaction. TRDY# is used in conjunction with

IRDY#. A data phase is complete on any PCI clock in

which both TRDY# and IRDY# are sampled as asserted.

During a read, TRDY# indicates that valid data is present

on AD[31:0]. During a write, it indicates that the target is

prepared to accept data. Wait cycles are inserted until

both IRDY# and TRDY# are asserted together.

D13

2.4.4

PCI Bus Interface Signals (Continued)

Signal Name

Ball No.

Type

Description

Mux

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