Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

TSI721 Fiches technique(PDF) 9 Page - Renesas Technology Corp

No de pièce TSI721
Description  Table of Contents
PDF  67 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

TSI721 Fiches technique(HTML) 9 Page - Renesas Technology Corp

Back Button TSI721 Datasheet HTML 5Page - Renesas Technology Corp TSI721 Datasheet HTML 6Page - Renesas Technology Corp TSI721 Datasheet HTML 7Page - Renesas Technology Corp TSI721 Datasheet HTML 8Page - Renesas Technology Corp TSI721 Datasheet HTML 9Page - Renesas Technology Corp TSI721 Datasheet HTML 10Page - Renesas Technology Corp TSI721 Datasheet HTML 11Page - Renesas Technology Corp TSI721 Datasheet HTML 12Page - Renesas Technology Corp TSI721 Datasheet HTML 13Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 67 page
background image
Tsi721 Datasheet
9
April 4, 2016
Integrated Device Technology
• Single virtual channel, VC0
• Single traffic class, TC0
— Generates only PCIe posted/non-posted TLPs with TC0
— Generates only PCIe Cpl/CplD TLPs with TC matching their requests
— Accepts PCIe TLPs with any TC
•Four BARs
— Prefetchable BAR with 32- or 64-bit addressing for PCIe-to-S-RIO bridging
— Non-prefetchable BAR with 32- or 64-bit addressing for PCIe-to-S-RIO bridging
— Non-prefetchable BAR with 32-bit addressing for PCIe MWr to S-RIO doorbell bridging
— Non-prefetchable BAR with 32-bit addressing for Tsi721 internal register access
• Initial credit advertisement programmable through EEPROM
• Dynamic control of credits through registers
• Starvation prevention based on flow control credit updates
• Large buffers
— 12 KB/2 KB/12 KB input buffers for up to 127 posted/non-posted/completion TLPs
— 12 KB/2 KB/12 KB output buffers for up to 128 posted/non-posted/completion TLPs
• Debug features
— Slave analog loopback through a control register
— Slave loopback using TS1/TS2 ordered sets
— Master loopback
— Internal error reporting
— ECC protection on internal memories
1.2.2
S-RIO Features
• S-RIO 2.1 standard compliant
• 5/3.125/2.5/1.25 Gbaud link speed
• x4/x2/x1 link width
• 34-, 50-, and 66-bit addressing
• 16 destID filters
• 8 S-RIO flows
• 9-KB ingress buffer (32 x 288)
• 9-KB egress buffer (32 x 288)
• Lane reversal
• Lane polarity inversion
1.2.3
Bridging Features
• Store and forward from PCIe to S-RIO
• Store and forward from S-RIO to PCIe
• Line rate support for 64 byte and larger packets
• 32 outstanding PCIe requests to root complex



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67


Fiches technique Télécharger

Go To PDF Page


Lien URL



ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Lien vers la fiche technique    |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com