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PSD4235G2V-10UI Fiches technique(PDF) 46 Page - STMicroelectronics

No de pièce PSD4235G2V-10UI
Description  Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
PDF  100 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD4235G2V-10UI Fiches technique(HTML) 46 Page - STMicroelectronics

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
External Chip Select
The CPLD also provides eight External Chip Se-
lect (ECS0-ECS7) outputs that can be used to se-
lect external devices. Each External Chip Select
(ECS0-ECS7) consists of one product term that
can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 17.)
Figure 17. External Chip Select Signal
Figure 18. Handshaking Communication Using Input Macrocells
POLARITY
BIT
PORT PIN
ECS PT
ECS
To Port C or F
ENABLE (.OE) PT
DIRECTION
REGISTER
Port C or Port F
AI04927
MASTER
MCU
MCU-RD
MCU-RD
MCU-WR
SLAVE – WR
SLAVE – CS
MCU-WR
D [ 7:0]
D [ 7:0]
CPLD
DQ
QD
PORT A
DATA OUT
REGISTER
PORT A
INPUT
MACROCELL
PORT A
SLAVE – READ
SLAVE
MCU
RD
WR
AI02877C
PSD



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