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PSD4235G2V-10UI Fiches technique(PDF) 39 Page - STMicroelectronics |
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PSD4235G2V-10UI Fiches technique(HTML) 39 Page - STMicroelectronics |
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39 / 100 page ![]() 39/100 PSD4256G6V This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 12. PLD Diagram 8 INPUT MACROCELL and INPUT PORTS DIRECT MACROCELL INPUT TO MCU DATA BUS CSIOP SELECT SRAM SELECT SECONDARY NON-VOLATILE MEMORY SELECTS DECODE PLD PAGE REGISTER PERIPHERAL SELECTS JTAG SELECT CPLD PT ALLOC. MCELLA MCELLB DIRECT MACROCELL ACCESS FROM MCU DATA BUS 24 INPUT MACROCELL (PORT A,B,C) 16 OUTPUT MACROCELL PRIMARY FLASH MEMORY SELECTS 12 PORT D and PORT F INPUTS TO PORT A TO PORT B DATA BUS 16 8 8 4 3 1 2 1 EXTERNAL CHIP SELECTS TO PORT C or PORT F 8 82 16 82 24 OUTPUT MACROCELL FEEDBACK AI04924B |
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