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S5320 – PCI Match Maker: Operation Registers

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

Data Sheet

OPERATION REGISTERS

All S5320 control and communications are performed

through two register groups: PCI Operation Registers

Add-On Operation Registers. Some registers in both

groups are accessible from both buses. This chapter

describes the PCI Operation Register set first and then

the Add-On Operation Register set for easier under-

standing. An access to a register common to both

buses at the same time is not allowed. Unpredictable

behavior may occur.

PCI BUS OPERATION REGISTERS

The PCI bus operation registers are mapped as 6

DWORD registers located at the address space (I/O or

memory) specified by Base Address Register 0. These

locations are the primary method of communication

between the PCI and Add-On buses. It is NOT recom-

mended to read or write from an undefined address.

The read results and write effects cannot be guaran-

teed. Table 28 lists the PCI Bus Operation Registers.

Note: Absolute register address locations are acquired by adding BADR0 to the “address offset” listed above.

Table 28. Operation Registers - PCI Bus

Address Offset

Abbreviation

0Ch

OMB

Outgoing Mailbox Register

1Ch

IMB

Incoming Mailbox Register

34h

MBEF

Mailbox Empty/Full Status Register

38h

INTCSR

Interrupt Control/Status Register

3Ch

RCR

Reset Control Register

60h

PTCR

Pass-Thru Configuration Register

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