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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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CS5320 Fiches technique(PDF) 41 Page - Applied Micro Circuits Corporation |
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CS5320 Fiches technique(HTML) 41 Page - Applied Micro Circuits Corporation |
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41 / 160 page  S5320 – PCI Match Maker: PCI Configuration Registers Revision 5.03 – June 14, 2006 AMCC Confidential and Proprietary DS1656 41 Data Sheet Cache Line Size Register (CALN) The cache line configuration register is used by bus masters implementing memory write and invalidate commands. The register defines the cache line size in double word (64-bit) increments. The S5320 is a target device not requiring cache. The register is hardwired to 0. Figure 12. Cache Line Size Register Register Name: Cache Line Size Address Offset: 0Ch Power-up value: 00h, hardwired Boot-load: not used Attribute: Read Only Size: 8 bits 00h 0 7 Cache Line Size (RO) |
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