LP3972 datasheet(53/59 Pages) NSC

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Application Note - LP3972 Reset Sequence (Continued)

POWER-ON TIMING

Symbol

Description

Min

Typ

Max

Units

Delay from V

CC_RTC assertion to nRSTO de-assertion

Delay from nBATT_FLT de-assertion to nRSTI assertion

100

µS

Delay from nRST de-assertion to SYS_EN assertion

Delay from SYS_EN assertion to PWR_EN assertion

125

Delay from PWR_EN assertion to nRSTO de-assertion

125

HARDWARE RESET SEQUENCE

Hardware reset initiates when the nRSTI signal is asserted

(low). Upon assertion of nRST the processor enters hard-

ware reset state. The LP3972 holds the nRST low long

enough (50 ms typ.) to allow the processor time to initiate the

reset state.

RESET SEQUENCE

nRSTI is asserted.

nRSTO is asserted and will de-asserts after a minimum

of 50 mS

The Applications processor waits for the de-assertion of

nBATT_FLT to indicate system power (V

IN) is available.

After system power (V

IN) is turned on, the LP3972 de-

asserts nBATT_FLT.

The Applications processor asserts SYS_EN, the

LP3972 enables the system high-voltage power sup-

plies. The Applications processor starts its countdown

timer.

The LP3972 enables the high-voltage power supplies.

Countdown timer expires; the Applications processor

asserts PWR_EN to enable the low-voltage power sup-

plies. The processor starts the countdown timer.

The Applications processor asserts PWR_EN, the

LP3972 enables the low-voltage regulators.

Countdown timer expires; If enabled power domains are

OK (I

2C read) the power up sequence continues by

enabling the processors 13 MHz oscillator and PLL’s.

10. The Applications processor begins the execution of

code.

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