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LP3972 Fiches technique(PDF) 31 Page - National Semiconductor (TI) |
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LP3972 Fiches technique(HTML) 31 Page - National Semiconductor (TI) |
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31 / 59 page ![]() I 2C Compatible Interface (Continued) V CC_COMM TARGET VOLTAGE 1 DUMMY REGISTER (CDTV1) V CC_COMM Target Voltage 1 Dummy Register (CDTV1) 8h’26 Write Only Bit 7 6 5 43210 Designation Reserved Output Voltage Reset Value 0 0 0 00000 Note: CDTV1 must be writable by an I2C controller. This is a dummy register V CC_COMM TARGET VOLTAGE 2 DUMMY REGISTER (CDTV2) V CC_COMM Target Voltage 2 Dummy Register (CDTV2) 8h’27 Write Only Bit 7 6 5 43210 Designation Reserved Output Voltage Reset Value 0 0 0 00000 Note: CDTV2 must be writable by an I2C controller. This is a dummy register and can not be read. This is a variable voltage supply to the internal SRAM of the Application processor. LDO5(V CC_SRAM) TARGET VOLTAGE 1 REGISTER LDO5(V CC_SRAM) Target Voltage 1 Register (SDTV1) 8H’29 Bit 7 6 5 4** 3** 2** 1** 0** Designation Reserved LDO 5 Output Voltage (L5OV) Reset Value 0 0 0 01011 Note: ** denotes one time factory programmable EPROM registers for default values LDO5(V CC_SRAM) Target Voltage 1 Register (SDTV1) 8h’29 Definitions Bit Access Name Description 7:5 — — Reserved 4:0 R/W B1OV Data Code 5h’0 5h’1 5h’2 5h’3 5h’4 5h’5 5h’6 5h’7 5h’8 5h’9 5h’A 5h’B 5h’C 5h’D 5h’E 5h’F Output Voltage — — — — — 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 Data Code 5h’10 5h’11 5h’12 5h’13 5h’14 5h’15 5h’16 5h’17 5h’18 5h’19 5h’1A 5h’1B 5h’1C 5h’1D 5h’1E 5h’1F Output Voltage 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 www.national.com 31 |
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