LP3972 datasheet(32/59 Pages) NSC

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2C Compatible Interface (Continued)

LDO5(V

CC_SRAM) TARGET VOLTAGE 2 REGISTER

LDO5(V

CC_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A

Bit

43210

Designation

Reserved

LDO 5 Output Voltage (L5OV)

Reset Value

01011

LDO5(V

CC_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A Definitions

Bit

Access

Name

Description

7:5

—

Reserved

4:0

R/W

B1OV

Data Code

5h’0

5h’1

5h’2

5h’3

5h’4

5h’5

5h’6

5h’7

5h’8

5h’9

5h’A

5h’B

5h’C

5h’D

5h’E

5h’F

Output Voltage

—

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

Data Code

5h’10

5h’11

5h’12

5h’13

5h’14

5h’15

5h’16

5h’17

5h’18

5h’19

5h’1A

5h’1B

5h’1C

5h’1D

5h’1E

5h’1F

Output Voltage

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

CC_MVT is low tolerance regulated power supply for the application processor ring oscillator and logic for communicating to the

LP3972. V

CC_MVT is enabled when SYS_EN is asserted and disabled when SYS_EN is deasserted.

LP3972 Fiches technique(PDF) 32 Page - National Semiconductor (TI)

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