STE2004 datasheet(59/66 Pages) STMICROELECTRONICS

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STE2004

Figure 73. 68000-series Parallel interface timing

Figure 74. 8080-series parallel Interface timing

Table 23 Electrical Characteristics (continued)

AC OPERATION (continued)

(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

PARALLEL INTERFACE

TCYC

System Cycle Time

VDD1 = 1.7V; Read & Write

125

TCLW

Control Low Pulse Width (WR)

TCHW

Control High Pulse Width (WR)

TCLR

Control Low Pulse Width (RD)

TCHR

Control High Pulse Width (RD)

TEWHW

Enable High Pulse Width (Write)

TEWLW

Enable Low Pulse Width (Write)

TEWHR

Enable High Pulse Width (Read)

TEWLR

Enable Low Pulse Width (Read)

TSU(A)

Address Set-up Time

TH(A)

Address Hold Time

TSU1

Data Set-Up Time

TH1

Data Hold Time

TSU2

Read Access Time

TH2

Output Disable Time

D/C

R/W

D0 to D7

(Write)

D0 to D7

(Read)

tSU2

tH2

tSU1

tCYC

tH(A)

tSU(A)

tEWHR, tEWHW

tEWLR, tEWLW

tH1

D/C

WR, RD

D0 to D7

(Write)

D0 to D7

(Read)

tSU2

tH2

tSU1

tCYC

tH (A)

tSU(A)

tCLR , tCLW

tCHR , tCHW

tH1

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