LSM6DSO datasheet(19/172 Pages) STMICROELECTRONICS

No de pièce	LSM6DSO

Description	iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope

PDF	172 Pages

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Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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Slave

SAK

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred

per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive

another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to

force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and

releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive

because it is performing some real-time function) the data line must be left HIGH by the slave. The master can

then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a

STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge.

LSM6DSO

I²C/SPI interface

DS12140 - Rev 2

page 19/172

LSM6DSO Fiches technique(PDF) 19 Page - STMicroelectronics