SCAS641

– JULY 2000

3

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

3V48(0)/SelA

25

I/O

Dual function 3.3 V, Type 3, 48-MHz clock output that latches the state of SelA during power up

3V48(1)/SelB

26

I/O

Dual function 3.3 V, Type 3, 48-MHz clock output that latches the state of SelB during power up

3V66[0

–3]

30, 31, 34, 35

O

3.3 V, Type 5, 66-MHz clock outputs

3VMREF

55

O

3.3 V, Type 5, 50/66-MHz memory clock output

3VMREF

54

O

3.3 V, Type 5, 50/66-MHz memory clock output (180 out of phase with 3VMREF)

GND

1, 7, 13, 19,

24, 32, 33, 37,

40, 46, 53

Ground for core and HCLK/HCLK, 3VMREF/3VMREF, 3V48, 3V66 and PCI outputs

HCLK[1

–4]

42, 45, 48, 51

O

Type X1, host clock outputs

HCLK[1

–4]

41, 44, 47, 50

O

Type X1, host complementary clock outputs

I_REF

39

Special

Current reference pin for the host clock pairs. I_REF uses a fixed precision resistor tied to ground

to establish the appropriate current.

PCI[0

–9]

8, 9, 11, 12,

14, 15, 17, 18,

20, 21

O

3.3 V, Type 5, 33-MHz PCI clock outputs

PWRDWN

28

I

Power down for complete device with HOST at 2 IREF, HCLK not driven and all other outputs

forced low.

REF0/MultSel0

2

I/O

Dual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel0 is latched

during power up. MultSel0 configures the IOH amplitude (and thus the VOH swing amplitude) of

the HCLK pair outputs.

REF1/MultSel1

3

I/O

Dual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel1 is latched

during power up. MultSel1 configures the IOH amplitude (and thus the VOH swing amplitude) of

the HCLK pair outputs.

SEL100/133

23

I

Active low LVTTL level logic select. SEL100/133 is used for enabling 100/133 MHz. Low=100

MHz, high=133 MHz

SPREAD

52

I

LVTTL level logic select. SPREAD pin enables/disables the spread spectrum for the

HCLK/HCLK, 3VMREF/3VMREF, 3V66 and PCI outputs.

VDD3.3V

4, 10, 16, 22,

27, 29, 36, 38,

43, 49, 56

I

3.3-V power for core and the HCLK/HCLK, 3VMREF/3VMREF, 3V48, 3V66, and PCI outputs.

XIN

5

I

Crystal input

– 14.318 MHz

XOUT

6

O

Crystal output

– 14.318 MHz