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CDC930 Fiches technique(PDF) 10 Page - Texas Instruments

No de pièce CDC930
Description  133-MHz DIFFERENTIAL CLOCK SYNTHESIZER / DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
PDF  17 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

CDC930 Fiches technique(HTML) 10 Page - Texas Instruments

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SCAS641
– JULY 2000
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0 C to 85 C (continued)
3VMREF/3VMREF (Type 5) CL = 30 pF, RL = 500
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
3VMREF/3VMREF clock
f(3VMREF/3VMREF) = 50 MHz
20
20.4
ns
tc
period†
f(3VMREF/3VMREF) = 66 MHz
15
15.3
ns
tjit(cc)
Cycle to cycle jitter
f(3VMREF/3VMREF) = 66 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
250
ps
tdc
Duty cycle
f(3VMREF/3VMREF) = 66 MHz
45%
55%
tsk(o)
3VMREF/3VMREF output
skew
3VMREF/
3VMREF
3VMREF/
3VMREF
f(3VMREF/3VMREF) = 66 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
250
ps
t(off)
3VMREF/3VMREF clock
to PCI offset
3VMREF/
3VMREF
PCIx
f(3VMREF/3VMREF) = 66 MHz,
Measured points at 1.5 V,
Measured at rising edges
3
ns
tr
Rise time
VO = 0.4 V to 2.4 V
0.5
2
ns
tf
Fall time
VO = 0.4 V to 2.4 V
0.5
2
ns
† The average over any 1– s period of time is greater than the minimum specified period.
3V66 (Type 5, No SSC), CL = 30 pF, RL = 500
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
3V66 clock period†
f(3V66)= 66 MHz
15.03
ns
tjit(cc)
Cycle to cycle jitter
f(3V66) = 66 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
300
ps
tdc
Duty cycle
f(3V66) = 66 MHz
45%
55%
tsk(o)
3V66 output skew
3V66x
3V66x
f(3V66) = 66 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
250
ps
t(off)
3V66 clock to PCI
3V66x
PCIx
f(3V66) = 66 MHz,
Measured points at 1.5 V,
Measured at rising edges
1.5
3.5
ns
tr
Rise time
VO = 0.4 V to 2.4 V
0.5
2
ns
tf
Fall time
VO = 0.4 V to 2.4 V
0.5
2
ns
† The average over any 1– s period of time is greater than the minimum specified period.
PCI (Type 5), CL = 30 pF, RL = 500
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
PCI clock period†
f(PCI)= 33.3 MHz
30.06
ns
tjit(cc)
Cycle to cycle jitter
f(HCLK) = 100 or 133 MHz
500
ps
tdc
Duty cycle
f(PCI) = 33.3 MHz
45%
55%
tsk(o)
PCI output skew
PCIx
PCIx
f(PCI) = 33.3 MHz
500
ps
tr
Rise time
VO = 0.4 V to 2.4 V
0.5
2
ns
tf
Fall time
VO = 0.4 V to 2.4 V
0.5
2
ns
† The average over any 1– s period of time is greater than the minimum specified period.



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