SCAS641

– JULY 2000

9

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

vover

Overshoot‡

HCLK/HCLK 0.7 V ampli-

VOH+200

mV

vunder Undershoot‡

tude

VOL–200

mV

vover

Overshoot‡

Other clocks, CL = Worst

GND

–0.7

V

vunder Undershoot‡

,

L

case

VDD+0.7

V

tPZL

Output enable time to low

level

f(HCL) = 100 or 133 MHz,

SELA, SELB = H,

100

ns

tPZH

Output enable time to high

level

SEL100/133

HCLK/

,,

SEL100/133 L

H,

Rref = 475

100

ns

tPHZ

Output disable time from

high level

SEL100/133

HCLK

f(HCL) = 100 or 133 MHz,

SELA, SELB = H,

10

ns

tPLZ

Output disable time from low

level

,,

SEL100/133 H

L,

Rref = 475

10

ns

tPZL

Output enable time to low

level

f(HCL) = 100 or 133 MHz,

SELA, SELB = H,

10

ns

tPZH

Output enable time to high

level

SEL100/133

REF, 3V48

3VMREF,

,,

SEL100/133 L

H,

Rref = 475

10

ns

tPHZ

Output disable time from

high level

SEL100/133

,

3VMREF,

3V66, PCI

f(HCL) = 100 or 133 MHz,

SELA, SELB = H,

10

ns

tPLZ

Output disable time from low

level

,,

SEL100/133 H

L,

Rref = 475

10

ns

tstab

Stabilization time†

After power up

3

ms

† Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for

phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present a XIN. Until phase lock is obtained, the specifications

for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the

time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.

‡ These parameters are ensured by design and lab characterization, not 100% production tested.

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t

HCLK clock period†

f(HCLK) = 100 MHz

10

10.2

ns

tc

HCLK clock period†

f(HCLK) = 133 MHz

7.5

7.65

ns

tjit(cc)

Cycle to cycle jitter

f(HCLK = 100 or 133 MHz

200

ps

tdc

Duty cycle

f(HCLK) = 100 or 133 MHz crossing

point

45%

55%

tsk(o)

HCLK bus skew

HCLKx

HCLKx

f(HCLK) = 100 or 133 MHz crossing

point

150

ps

t

Pulse duration width

f(HCLK = 100 MHz

4.41

ns

tw

Pulse duration width

f(HCLK = 133 MHz

3.29

ns

tr

Rise time

‡

07V

VO = 0.14 V to 0.56 V

175

700

ps

tf

Fall time

‡

0.7 V

amplitude

VO = 0.14 V to 0.56 V

175

700

ps

tr, tf

Rise and fall time matching‡

am litude

2

(tr – tf)/(tr + tf)

20%

vcross

Cross point voltages‡

0.7 V

amplitude

f(HCLK) = 100 or 133 MHz

HCLK and HCLK

40%

VOH

55%

VOH

V

† The average over any 1– s period of time is greater than the minimum specified period.

‡ These parameters are ensured by design and lab characterization, not 100% production tested.